Page 91

Contents | 91 of 167

Download PDF | | Reference URL | Gallery View | Parent Record

Publication Type	Technical report
School or College	College of Engineering
Department	Computing, School of
Creator	Carter, Tony Marvin
Title	ASSASSIN: an assembly, specification and analysis system for speed-independent control-unit design in integrated circuits using path-programmable logic (PPL)
Date	1982-06
Description	Abstract: Numerous efforts have been made to automatically implement the control-units and datapaths of synchronous systems in integrated circuits. Speed-independent systems have not yet been extensively explored in the context of the integrated circuit. Presented in this thesis is a software system--ASSASSIN: an Assembly, Specification and Analysis System for Speed-Independent Control-Unit Design--which aids the systems designer in specification, simulation and implementation. PSL (Portable Standard LISP) is used as the implementation language for ASSASSIN. It is shown that the implementation of speed-independent control-units implemented using well-known techniques is feasible and shows that PPL is indeed amenable to CAD tool development. It also demonstrates the power and appropriateness of a PSL based environment for VLSI design.
Type	Text
Publisher	University of Utah
Subject	path-programmable logic; integrated circuits; Portable standard LISP; VLSI design
Subject LCSH	Integrated circuits--Research; Integrated circuits--Computer-aided design
Language	eng
Series	University of Utah Computer Science Technical Report
Relation is Part of	ARPANET
Format Medium	application/pdf
Format Extent	223,355,153 bytes
File Name	Carter-Assasin_A_CAD_System.pdf
Conversion Specifications	Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by LIMB™ for CONTENTdm display
ARK	ark:/87278/s6v14r1p
Setname	ir_computersa
ID	106839
Reference URL	https://collections.lib.utah.edu/ark:/87278/s6v14r1p

Page Metadata

Title	Page 91
Setname	ir_computersa
ID	106762
OCR Text	Show 18 Column Number , , , , , , , , , 1 222 2 o 2 345 Q 7 􁪽􋴹 9 0 1 234 5 Q 7 􁪽􋴹 9 0 1 2 3 I I I I I I I I I I I 1 1 I 1 1 A IIITI1III B ITIIIII1I C ITlll D ITIII E F 111' 12131 12PH5101 13171 141􁪽􋴱1 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I : : : : : : : : : : : : : : : : : : : : : : R I 19 01 WI Hi I NI 17 01 .1 12 IR-----------􁪽􋴭-1-----------11-1-IR---P-'-------', . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10---------------------P-------1---'-+-------0-SI -: :-:: :--::: :- ... :: :-: :-:: 4 1-1-1-1-1-1-IO--􁪽􋴭--------O---P---0-s---O-O-----11 - : : - : : :. - : 􁪽􋴺 :.: :.: : -._ : : : - : : - : : 3 1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-lo---1-P-------RI-1 Figure 13: Compilati􁪽􋵮n of the Scale-of-Two Loop Column Number ------------- 1 1 1 , 1 1 1 , , , 2 222 0 1 2 3 􁪽􋴵 5 b 7 ts g·O 1 2 3 4 5 0 7 􁪽􋴹 9 0 123 RI "9 I I I I I I I I I I I I I I I I 01 A I1lTlllII B ITlll1lll C ITlll D ITlll E F WI 1􁪽􋴱 111112131 121415101 13171 PH s I I I 1 1 I 1 1 I I I 1 I I I I 1 I Nt 17 1 1 I J I I I 1 1 I I I I I I I 01 : : : : : : : : : : : : : : : : : : : : : : : • I 13 1-11-1-1-------S-------P---3-----------------01-1 : : : : : : : : : :. : : : : : : : : : : : : : : 12 IR-----------P-1-----------11-1-IR---P-1-------" Figure 14: Compilation of the FORK Transition
Reference URL	https://collections.lib.utah.edu/ark:/87278/s6v14r1p/106762