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Show 44 circuit designer can build larger cells from the PPL primitive cells 14. , Concepts of Path Programmable Logic or create his own special function cells as needed. PPL is very similar to the SLA (72). One is given a basic set of . storage elements {4-wire latch, Set/Reset Flip-Flop, Read-Enabled Set/Reset Flip-Flop, Write-Enabled Set/Reset Flip-Flop, Read/Write- Enabled Set/Reset Flip-Flop}, a basic set of gate elements {inverter}, a basic set of row elements {1, 0, S, R, +, -L, -R}, and a set of sets of other necessary cells {a set of row loads, a set of column loads, a set of cap cells, a set of connection cells, a set of break cells}. These sets may be augmented in any way, and indeed the overall PPL cell set (the union of all these sets) may also be augmented to include such things as macros by adding additional ses of elements. NMOS PPL is implemented using negative logic in the columns and positive logic in the rows. The column wires are true when pulled low and the row wires are true when left to be pulled high by a row load. The rows are distributed AND gates and the columns are distributed OR gates. As one constructs a path from one storage element or gate to another, one picks up inputs to the path (AND or OR gate) as necessary in the logic design. PPL Programs are constructed by placing the appropriate storage .elements and gates and then constructing appropriate paths bet'Ween '" them. One may think of the path as being an AND-OR gate, 'With the knowledge that a path may have only ohmic contacts and therefore be a |
