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Show 62 er absolute or relative cell sizes. It merely defines which PPL cells will be used to represent certain required elements of the controlunit. In order to perform the compilation, one must taXe into account the topological constraints the PPL cells place on placement and routing (path construction). If storage and gate elements are to be stacked above one another, care must be taken to assure that ·their control and output signals do not conflict. If more than two levels of storage or gate elements are to be usec , then the compiler will require some rather sophisticated routing algorithms in order to get required signals to and from t?oth state variables and outputs. The PPL programmer (designer) learns various tricks as he builds integrated circuits using the PPL cells. Some of these tricks could oe used to perform some speed, power or size optimization in the generation of compiled PPL programs. The. inclUsion of .euen optimizations incurs additional overhead in PPL program generation from SICUDL and substtial effort in programming the code generator. In addition, some optimizations are possible only in restricted cases and the code generator must be intelligent enough to discern whether these cases apply or not to any given ·construct. The ASSASSIN Compilation Algorithm Taking into account the above conSiderations, the follOwing algorithm was developed for compiling SICUDL programs into PPL programs. First, in order to elilllinate the complex router needed in order to do greater than linear compilation (compilation to only two |
