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Show 48 This constitutes dumping the contents of the register onto the bus. Row 7 appears very strange. It has a SET row element in it under column 1, but column 1 contains no flip-nope This is because the SET row element is being used to pull the right hand wire of column 1 to ground. Thus, the SET row element in row 7 distributes an enable to the register telling it to read and store the state of the bus. Row 8 also is strange. It has a RESET row element in it under column 1, but column 1 contains no nip-nop. This is because the 4.2 The NMOS Design Rules !!2£ Process RESET row element is being used to pull the left hand wire of column 1 to ground. Thus, the RESET row element in row 8 distributes an enable to the register telling it to send its contents to the bus. These non-standard uses of PPL cells to implement circuits are evidences of deficiencies in the logical (not the physical) cell set. While correct electrically, they do not function in the standard way. Logically they ar-e a new element. Thus, proper standard use of the PPL can be maintained if a new cell is added to the library. This is merely another argument that PPL is different from the SLA in that it needs to have a dynamically growing cell set to meet its requirement that the PPL program represent the logic of the circuit. The NMOS process assumed in designing this Speed-Independent PPL Ce.ll Set and the Standard Synchronous ?PL Cell Set developed at the '" Un! versity of Utah .by the VLSI Research Group is a very conservative one. It uses 6 micron minimum diffusion and polysilicon feature sizes |
