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Show 49 4.3 Design of the Standard Synchronous PPL and 7 micron minimum metal feature sizes. The implementation of PPL in such a conservative process helps to assure that many fabrication facilities can successfully build circuitS designed using PPL. The process is a standard 7 mask, 6-micron, silicon gate NMOS process including the use of buried contacts. The design rules were devised such that many fabrication facilities should have no trouble aligning, printing or etching patterns. In addition, the design rules are overly conser-vative so that circuits designed at the 6-micron design rules can be direqtly scaled to 5-micron circuits while retaining the same measure of alignment and printing tolerances found in the 6-micron process. Appendix B contains a complete description of these design rules. The Standard 6-Micron NMOS Synchronous PPL consists of the following sets of elements: storage elements, gate elements, row elements, column load elements, termination and connection elements. This section will list only the names and functions of each cell in the Standard Synchronous PPL Cell Set. Appendix C contains a complete description of the SpeedIndependent subset of the complete ?PL cell set as at present constituted. It includes graphical representations of the cells, cell schematics, cell composites, and other information pertinent to each cell. Since the PPL cell set is dynamic in nature, such documentation is quickly outdated by additions to the cell set. |
