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Publication Type	Technical report
School or College	College of Engineering
Department	Computing, School of
Creator	Carter, Tony Marvin
Title	ASSASSIN: an assembly, specification and analysis system for speed-independent control-unit design in integrated circuits using path-programmable logic (PPL)
Date	1982-06
Description	Abstract: Numerous efforts have been made to automatically implement the control-units and datapaths of synchronous systems in integrated circuits. Speed-independent systems have not yet been extensively explored in the context of the integrated circuit. Presented in this thesis is a software system--ASSASSIN: an Assembly, Specification and Analysis System for Speed-Independent Control-Unit Design--which aids the systems designer in specification, simulation and implementation. PSL (Portable Standard LISP) is used as the implementation language for ASSASSIN. It is shown that the implementation of speed-independent control-units implemented using well-known techniques is feasible and shows that PPL is indeed amenable to CAD tool development. It also demonstrates the power and appropriateness of a PSL based environment for VLSI design.
Type	Text
Publisher	University of Utah
Subject	path-programmable logic; integrated circuits; Portable standard LISP; VLSI design
Subject LCSH	Integrated circuits--Research; Integrated circuits--Computer-aided design
Language	eng
Series	University of Utah Computer Science Technical Report
Relation is Part of	ARPANET
Format Medium	application/pdf
Format Extent	223,355,153 bytes
File Name	Carter-Assasin_A_CAD_System.pdf
Conversion Specifications	Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by LIMB™ for CONTENTdm display
ARK	ark:/87278/s6v14r1p
Setname	ir_computersa
ID	106839
Reference URL	https://collections.lib.utah.edu/ark:/87278/s6v14r1p

Page Metadata

Title	Page 76
Setname	ir_computersa
ID	106747
OCR Text	Show 63 ban􁪽􋵳s of sto􁪽􋵡age and/or gate elements), all states, input and temporary variables will be placed in a ..lower band of the PPL program and all output variables will be placed in an upper band.' This divides the PPL program into four distinct regions. The bottom region is located below tne ban􁪽􋵯 of state, input ana temporary variables and is to be used for implementing transitions only. The next region will be fillea by state lat􁪽􋵨hes an􁪽􋵩 input/temporary gates (inverters). All boolean expressions will be compiled above the state latches and input/temporary gates and below the output gates and latches as will all outputs. Figure 9 shows this global organization • . --------------------------------􁪽􋴭------------. Output Latches and Gates Boolean Expressions and Output -Generation State Latches, Input/Temp Gates Transitions ,---------------------------------------------, Figure 9: Block Structure of PPL Programs Produced by ASSASSIN Gi ven. this global block structure wi thin "..hich to work, the following aspects or the algorithm remain to !:Ie defined: - Placement of State LatGhes,
Reference URL	https://collections.lib.utah.edu/ark:/87278/s6v14r1p/106747