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Publication Type	technical report
School or College	College of Engineering
Department	Computing, School of
Creator	Kyrobie, Dean Cody
Title	Accurate capacitance and resistance extraction
Date	1993-03
Description	A novel approach to solving the accurate capacitance and resistance extraction problem in integrated circuits is presented as a combination of a custom language and a kit of circuit analysis primitives. This approach is targeted toward the analysis of circuit interconnect and the determination of fringing capacitance in digital integrated circuits with orthogonal layout. Such issues as netlist simplification and the granularity of the extraction report may be more completely addressed when they are solved programmatically Features exist to manage efficiently the quantity of data that constitutes a node-to-node table of capacitance and the complexity of the functions that accept circuit measurements as inputs and yield capacitive coupling values as outputs. A methodology is suggested to provide a more rapid analysis of circuit interconnect, which consists of building tabular data for the many cases of geometry interactions and a sequencing method for traversing the data. The program control allows for arbitrarily complex constraints to be imposed on the analysis so long as they can be expressed in the imperative language. This allows for a trade-off between accuracy and run time, for special critical paths to be designated for analysis, for interactive queries following the extraction, for special reports or data sets to be generated, and for unusual electrical relationships to be explored.
Type	Text
Subject	integrated circuits; electric resistance
Language	eng
Bibliographic Citation	Kyrobie, D. C. (1993). Accurate capacitance and resistance extraction.
Series	University of Utah Computer Science Technical Report
Relation is Part of	ARPANET
Format Medium	application/pdf
Format Extent	89,643,951 bytes
File Name	Kyrobie-Accurate_Capacitance.pdf
Conversion Specifications	Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display
ARK	ark:/87278/s6rv2q0d
Setname	ir_computersa
ID	101784
Reference URL	https://collections.lib.utah.edu/ark:/87278/s6rv2q0d

Page Metadata

Title	Page 137
Setname	ir_computersa
ID	101782
OCR Text	Show 127 10. Nanz, G., Dickinger, P., AND Selberherr, S. Calculation of contact currents in device simulation. IEEE Trans. Computer-Aided Design CA0-11, 1 (Jan. 1992), 128-136. 11. Kernighan, B. W., AND Pike, R. The Unix Programming Environment, Prentice-Hall, Englewood Cliffs, NJ., 1984. 12. Barna, A. Very High Speed Integrated Circuits Technologies and Tradeoffs. John Wiley & Sons, New York, NY., 1981. 13. Hewlett Packard CMOS Process Design Guide. Hewlett Packard Inc. San Jose, Ca. 14. Su, S., Rao, V., AND Trick, T. HPEX: A hierarchical parasitic circuit extractor. In Proceedings of the 24th Design Automation Conference (June 1987). IEEE, New York, 1987, pp. 566-569. 15. Nabors, K., AND White, J. FastCap: A multipole accelerated 3- dimensional capacitance extraction program. IEEE Trans. ComputerAided Design, CAD-10, 11 (Nov. 1991), 1447-1459. 16. Raghavan, V., Bracken, J., AND Rohrer, R., AWESpice: a general tool for the accurate and efficient simulation of interconnect problems. In Proceedings of the 29th Design Automation Conference (June 1992). IEEE, New York, pp. 87-92. 17. Huang, X., Raghavan, V., AND Rohrer, R. AWEsim: A program for the efficient analysis of linear(ized) circuits, In Proceedings of the International Conference on Computer-Aided Design (November 1990). IEEE, New York, 1990, pp. 534-537. 18. Lee, J. Y., AND Rohrer, R. A. AWEsymbolic: Compiled analysis of linear(ized) circuits using asymptotic waveform evaluation. In Proceedings of the 29th Design Automation Conference (June 1992). IEEE, New York, 1992, pp. 213-218. 19. Matthei, G. L., Chinn, G., Plott, C. H., AND Dagli, N. A simplified means for computation of interconnect distributed capacitances and inductances. Journal of Computer Aided Design, (Feb. 1992). 20. Ling, D. D., Kim, S., AND White, J. A boundary-element approach to transient simulation of three-dimensional integrated circuit interconnect. In Proceedings of the 29th Design Automation Conference (June 1992). IEEE, New York, 1992, pp. 93-98.
Reference URL	https://collections.lib.utah.edu/ark:/87278/s6rv2q0d/101782