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Show 24 segments, and two paths are modeled as if they were coupled by floating capacitors in parallel between them.22 Recent advances in analog simulation have demonstrated that computational accelerations between two and five orders of magnitude are possible if the model is simulated with asymptotic waveform evaluation (AWE) instead of piece-wise linear analysis. 17, 1a This has the effect of shifting the bottleneck of circuit analysis to the tools that extract the coupling values from the physical layout and makes the subject of this thesis more interesting. The simplest case to extract is one of a single path with a width, a length and a layer designation. The width and length can be measured to give area and perimeter whereas the thickness and the material of the path are determined from a suitable technology file. Capacitance to substrate is determined as a function of layer, area and perimeter, and the path is simply modeled as a capacitor to ground. An analysis of the voltage spikes on a line requires a measurement of the capacitive coupling between lines and a summing of the voltages incurred as a function of the dv/dt of the waves on the lines. Over the next few examples a series of short ACRE examples will be presented, which lead up to that. In Figure 3.1 is a case where three parallel paths are analyzed for length and width to determine capacitance to the substrate. When path information is imported through CIF or GDSII stream, then length, width and layer information are directly available. As a way of introducing ACRE code, Figure 3_.1 also has the ACRE statement to print the length and width of each of the three paths. |
