| OCR Text |
Show 3 incurred from neighboring lines can introduce transient voltage spikes that cause a circuit to fail. As devices shrink and path lengths increase, the need to determine fringing capacitance grows to become the paramount problem. ACRE provides a flexible solution with an interpreted language that can be programmed to any arbitrary complexity to balance analysis run times and result accuracy. Various capacitance formulae are discussed in Chapter 2 and a progression of measurement techniques is the subject of Chapter 3. The Potential Data Explosion There are several ways to reduce the count of nodes in a circuit and simplify the problem of analysis. The simplest traditional way of defining a node in a circuit is to associate all geometries and paths that are electrically connected as one node. This can be a node that passes through a number of materials between all of its connection points. Resistance for such a node is a meaningless concept; the node has only capacitance. The resistance in the timing estimate is in the driving transistor's gate with perhaps an extra nominal amount to compensate for the lack of resistance attributed to the node. The notion of highlighting a node applies to this model where only transistors, resistors, diodes, capacitors and gaps separate nodes. Its advantage is that it provides a minimum node count. For high speeds (> 50 MHZ), small device sizes (< 1 micron), or long runs(> 500 microns), this model may be too inaccurate. When the nodes in a circuit are large, they no longer behave in an ideal |
