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Show 6 are inherently faster because they reduce the capacitance to substrate. The design of this thesis is to help determine capacitance by providing a rich set of interconnect measurement and fringing analysis primitives. Other tools approximate capacitance between geometries as additional capacitance to substrate or evaluate cumulative delay through a circuit, a but these approaches do not solve the coupling problems between nodes. Linear RC delay modeling provides results that are easily programmed into the circuit models used here. 7,8,9 Predetermined values for contact resistance, for example, are readily available.1o An analysis of a node's capacitance to the substrate has the two facets of nodal area and nodal perimeter, and the importance of each varies with the frequency of the signals in the circuit. On a transistor source or drain an analysis of perimeter capacitance again divides into what perimeter is common to the transistor gate and what is not. Gate capacitance again varies with the transistor state: on, off, or in between. Where the nodes abut and an analysis of perimeter requires a merge first, ACRE has a Boolean operation to derive a single, larger polygon to analyze. More complex Boolean operations (and, subtract, xor) require preprocessing not available in ACRE. One problem in determining capacitance among neighboring geometries is that the relationships do not map to the ·formulae of parallel plates. One approach in wide use at one large American IC manufacturer of microprocessors has been to estimate the interconnect capacitance by simply categorizing the separation between paths into 'near', 'medium' or 'far'. The |
