| OCR Text |
Show REFERENCES 1. Matthaei, G. L., Chinn, G. C., Plott, C. H., AND Dagli, N. A simplified means for computation of interconnect distributed capacitances and inductances. IEEE Trans. Computer-Aided Design CAD-11, 4 (April 1992), 513-523. 2. Wang, Z., AND Wu, Q. A two-dimensional resistance simulator using the boundary element method. IEEE Trans. Computer-Aided Design CAD- 11, 4 (April 1992), 497-504. 3. Chiang, K. Resistance extraction and resistance calculation in GOALIE2. In Proceedings of the 26th Design Automation Conference (June 1989). IEEE, New York, 1989, pp. 682-685. · 4. van der Meijs, N. P., AND van Genderen, A. J. An efficient finite element method for submicron IC capacitance extraction, In Proceedings of the 26th Design Automation Conference (June 1989). IEEE, New York, 1989, pp. 678-681. 5. Weste, N., AND Eshraghian, K. Principles of CMOS VLSI Design A Systems Perspective. Addison-Wesley, Reading, MA., 1985. 6. Vlach, J., Barby, J. A., Vannelli, A., Talkhan, T., AND Shi, C. J. Group delay as an estimate of delay in logic. IEEE Trans. Computer-Aided Design CAD-1 0, 7 (July 1991 ), 949-953. 7. Deng, A. AND Shiau, Y. G·eneric linear RC delay modeling for digital CMOS circuits. IEEE Trans. Computer-Aided Design CAD-9, 4 (April 1990), 367-376. 8. Ciesielski, M. J. Layer assignment for VLSI interconnect delay minimization. IEEE Trans. Computer-Aided Design CAD-8, 6 (June 1989), 702-707. 9. Passlack, M., Uhle, M., AND Elschner, H. Analysis of propagation delays in high-speed VLSI circuits using a distributed line model. IEEE Trans. Computer-Aided Design CAD-9, 8 (Aug. 1990), 821-826. |
