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Show 80 The Checkmate Approach to Parasitic Capacitance The origin of Checkmate comes from Texas Instruments Corp., -where it began as a program to do circuit extraction for the purpose of layout versus schematic verification and layout verification in general. It was built to recognize objects in layout and associate schematic symbols and nets with them. To analyze layout in Checkmate, the problem must be reduced to one of measurements, which are the results of Boolean operations. This approach is used when layout is analyzed to determine a net list, and the layout is processed to find devices such as transistors and contacts. In Figure 4.1 is a typical Checkmate approach to finding an overlap capacitor, measuring the capacitance, and assigning the nodes. The new device is given a name, a type, a pair of terminals, and a capacitive value. The Checkmate approach is sufficient to identify deliberate devices like transistors, resistors and intentional capacitors, but it does not easily transfer to unintentional devices. Within a transistor the unintentional parasitic values are normally implied from a technology model, and Checkmate does not need to determine them. The most important part of the formula is the constant 0.400E-15, which is the capacitance in farads per square micron between first metal and poly. The capacitance between these two interconnect paths is determined as a function of overlap area times this constant. To contrast this to the ACRE approach, the equivalent ACRE definition is given below. foreach(layer(MET1, POLY) met1, poly) { foreach(center(met1, poly) met1_center, poly_center) { |
