Accurate capacitance and resistance extraction

A novel approach to solving the accurate capacitance and resistance extraction problem in integrated circuits is presented as a combination of a custom language and a kit of circuit analysis primitives. This approach is targeted toward the analysis of circuit interconnect and the determination of fringing capacitance in digital integrated circuits with orthogonal layout. Such issues as netlist simplification and the granularity of the extraction report may be more completely addressed when they are solved programmatically Features exist to manage efficiently the quantity of data that constitutes a node-to-node table of capacitance and the complexity of the functions that accept circuit measurements as inputs and yield capacitive coupling values as outputs. A methodology is suggested to provide a more rapid analysis of circuit interconnect, which consists of building tabular data for the many cases of geometry interactions and a sequencing method for traversing the data. The program control allows for arbitrarily complex constraints to be imposed on the analysis so long as they can be expressed in the imperative language. This allows for a trade-off between accuracy and run time, for special critical paths to be designated for analysis, for interactive queries following the extraction, for special reports or data sets to be generated, and for unusual electrical relationships to be explored.