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Publication Type	technical report
School or College	College of Engineering
Department	Computing, School of
Creator	Gu, Jun
Title	Parallel Algorithms and Architectures for Very Fast AI Search
Date	1989-08
Description	A wide range of problems in natural and artificial intelligence, computer vision, computer graphics, database engineering, operations research, symbolic logic, robot manipulation and hardware design automation are special cases of Consistent Labeling Problems (CLP). CLP has long been viewed as an efficient computational model based on a unit constraint relation containing 2N-tuples of units and labels which specifies which N-tuples of labels are compatible with which N-tuples of units. Due to high computation cost and design complexity, most currently best-known algorithms and computer architectures have usually proven infeasible for solving the consistent labeling problems. Efficiency in CLP computation during the last decade has only been improved a few times. This research presents several parallel algorithms and computer architectures for solving CLP within a parallel processing framework. For problems of practical interest, 4 to 10 orders of magnitude of efficiency improvement can be easily reached. Several simple wafer scale computer architectures are given which implement these parallel algorithms at a surprisingly low cost.
Type	Text
Subject	parallel algorithms; CLP; consistent labeling problems; computer programming; computer science
Language	eng
Bibliographic Citation	Gu, J. (1989). Parallel algorithms and architectures for very fast AI search.
Series	University of Utah Computer Science Technical Report
Relation is Part of	ARPANET
Format Medium	application/pdf
Format Extent	116,876,932 bytes
File Name	Gu-Parallel_Algorithms.pdf
Conversion Specifications	Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display
ARK	ark:/87278/s69s3s9x
Setname	ir_computersa
ID	99969
Reference URL	https://collections.lib.utah.edu/ark:/87278/s69s3s9x

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Title	Page 313
Setname	ir_computersa
ID	99961
OCR Text	Show 295 [81] P. V. Hentenryck. Constraint Satisfaction in Logic Programming. The MIT Press, Cambridge, 1989. [82] W. D. Hillis. The Connection Machine. The MIT Press, Cambridge, 1985. [83] G. E. Hinton. Relaxation and Its Role in Vision. PhD thesis, Univ. of Edinburgh, 1977. [84] G. E. Hinton and J. A. Anderson, editors. Parallel Models of Associative Memory. Lawrence Erlbaum Associates, Publishers, Hillsdale, New Jersey, [85] 1981. . G. E. Hinton and T. J. Sejnowski. Learning and Relearning in Boltzmann M achine. In D. E. Rumelhart and J. L. McClelland, editors, Parallel Distributed Processing: Explorations in the Microstructure of Cognition. Vol. 1: Foundations, chapter 7, pages 282-317. Volume 1, The MIT Press, Cambridge, 1986. [86] B. K. P. Horn and B. G. Schunck. Determining Optical Flow. Technical Report AI Memo 572, AI Lab, MIT, Apr. 1978. [87] E. Horowitz and S. Sahni. Fundamentals of Computer Algorithms. Computer Science Press, Rockville, 1978. [88] R. A. Hummel and S. W. Zucker. On the Foundations of Relaxation Labeling Processes. IEEE Trans. on Pattern Analysis and Machine Intelligence, PAMI-5(3):267-287, May 1983. [89] K. Hwang. Advanced Parallel Processing with Supercomputer Architectures. IEEE Proceedings, 75(10):1348-1379, Oct. 1987. [90] K. Hwang and F. A. Briggs. Computer Architecture and Parallel Processing. McGraw-Hill, New York, 1984. [91] K. Hwang, J. Ghosh, and R. Chowkwanyun. Computer Architectures for Artificial Intelligence Processing. IEEE Computer, 20(1):19-27, Jan. 1987. [92] R. R. Johnson. Critical Issues in Computer Architecture Design. 1987-1989. Private Communication. [93] R. R. Johnson. Discrete Wafer Scale Integration, pages 345-352. Elsevier Science Publishers B. V. (North-Holland), 1986. [94] R. R. Johnson. UN/PRO Silicon Circuit Board Series 2000. MOSAIC Systems Inc., Troy, Michigan. [95] R. R. Johnson. UN/PRO Silicon Circuit Board Series 3000. MOSAIC Systems Inc., Troy, Michigan. [96] R. R. Johnson. Elements of A Theory for Computer Performance. Aug. 1988. Unpublished Manuscript. [97] J. R. Josephson, B. Chandrasekaran, J. W. Smith Jr., and M. C. Tanner. A Mechanism for Forming Composite Explanatory Hypotheses. IEEE Trans. On Systems, Man, and Cybernetics, SMC-17(3):445-454, May/June 1987.
Reference URL	https://collections.lib.utah.edu/ark:/87278/s69s3s9x/99961