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Show APPENDIX B VLSI MODELS Various VLSI computational models have been proposed [5,22,21 ,12,107 ,14,13, 123,185,186,187,164,165,193,196]. There might be three main reasons for studying such models: firstly, they appear to have inherent theoretical interest; secondly, they provide a high level of abstraction at which to start the design of VLSI circuits, thus allowing one to think in algorithmic rather than electrical terms; finally, though they are not physically realistic, they allow one to estimate the order of growth of various parameters in terms of the size of the problem. In this overview below, only "standard features" will be introduced to the VLSI model. The interested reader is referred to [185) for more details on the practical significance of the model, and to [165) for an excellent introduction to the theoretical aspects of VLSI modeling. The basic parameters of any VLSI computation model are chip area and computation time. VLSI systems display a trade-off between these two parameters, each of which represents a well-defined cost aspect: chip area is a measure of fabrication cost and computation time is a measure of operating cost. A general feature of all proposed - and presumably of all future - VLSI models of computation is that a chip is viewed as a computation graph, whose vertices are called nodes and whose arcs are called wires. Nodes are, by and large, devices and are responsible for information processing, i.e., computation of Boolean functions; wires are just electrical connections, and are responsible for both transfer of |
