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Show 252 tree. These control signals decide four state transportation operations, transferdown( tree [level] , tree [level - 1]), back-transfer(tree [level] , tree [level - 1]), transfer-to-dra(L, tree[tree] and transfer-to-tree(tree[tree], L) . All the above operations can be completed in 0(1) time. The entire Parallel State Memory for the projected object size and label size can be implemented on a couple of chips [175). 7 .3.6 The Solution Memory The Solution Memory is designed to store solution labeling found during a CLP search. It consists of a Path Checker, a Solution Checker, a Memory Bank, an Address Counter and a Solution Counter. The Path Checker stores intermediate path information and monitors the continuity of the path. H a path is discontinued, a signal of PATH broken is sent. As soon as a full path (i.e., a solution) is found, this solution is delivered to the Solution Checker. Path Checker saves time since a path is checked without stopping the search process. The Solution Checker checks unambiguousness and completeness of a solution. If a solution qualifies, a ON E....solution signal is issued. Address Counter increments address where last solution is stored so that a new corning solution can be appropriately stored. Solution Counter tells Search Manager how many solutions have been found in this search branch. 7.3.7 The 1/0 Network The I/0 Network interfaces the CLPl architecture with a host computer. Its major function is to input (output) constraint elements into (out) the CLP1 machine. Since modern wafer-scale integration techniques (e.g., SHIP and WHIP) are used in our design, there are many alternatives that could be chosen to meet differ- |
