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Publication Type	technical report
School or College	College of Engineering
Department	Computing, School of
Creator	Gu, Jun
Title	Parallel Algorithms and Architectures for Very Fast AI Search
Date	1989-08
Description	A wide range of problems in natural and artificial intelligence, computer vision, computer graphics, database engineering, operations research, symbolic logic, robot manipulation and hardware design automation are special cases of Consistent Labeling Problems (CLP). CLP has long been viewed as an efficient computational model based on a unit constraint relation containing 2N-tuples of units and labels which specifies which N-tuples of labels are compatible with which N-tuples of units. Due to high computation cost and design complexity, most currently best-known algorithms and computer architectures have usually proven infeasible for solving the consistent labeling problems. Efficiency in CLP computation during the last decade has only been improved a few times. This research presents several parallel algorithms and computer architectures for solving CLP within a parallel processing framework. For problems of practical interest, 4 to 10 orders of magnitude of efficiency improvement can be easily reached. Several simple wafer scale computer architectures are given which implement these parallel algorithms at a surprisingly low cost.
Type	Text
Subject	parallel algorithms; CLP; consistent labeling problems; computer programming; computer science
Language	eng
Bibliographic Citation	Gu, J. (1989). Parallel algorithms and architectures for very fast AI search.
Series	University of Utah Computer Science Technical Report
Relation is Part of	ARPANET
Format Medium	application/pdf
Format Extent	116,876,932 bytes
File Name	Gu-Parallel_Algorithms.pdf
Conversion Specifications	Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display
ARK	ark:/87278/s69s3s9x
Setname	ir_computersa
ID	99969
Reference URL	https://collections.lib.utah.edu/ark:/87278/s69s3s9x

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Title	Page 312
Setname	ir_computersa
ID	99960
OCR Text	Show 294 [64] J. Gu and K. F. Smith. Fast Structured Design of VLSI Circuits. Technical Report UUCS-TR-88-024, Dept. of Computer Science, Univ. of Utah, Sept. 10 1988 (to appear in IEEE Transaction, 1989). [65] J. Gu. An Optimal, Parallel Discrete Relaxation Algorithm and Architecture. Technical Report UUCS-TR-88-006, submitted to IEEE Transactions for publication. [66) J. Gu and K. F. Smith. A Structured Approach for VLSI Circuit Design. IEEE Computer, to appear. [67) J. Gu and W. Wang. VLSI Architectures for Discrete Relaxation Algorithm. In T. C. Henderson, Discrete Relaxation Techniques, chapter 9, pages 111- 136. Oxford University Press, New York, 1989. [68) J. Gu. Ideas, Algorithms and Architectures for Very Fast AI Search. Unpublished Manuscript. [69] R. M. Haralick, L. S. Davis, A. Rosenfeld, and D. Milgram. Reduction Operations for Constraint Satisfaction. Information Sciences, 14:199- 219, 1978. [70] R. M. Haralick and G. Elliot. Increasing Tree Search Efficiency for Constraint Satisfaction Problems. Artificial Intelligence, 14:263-313, 1980. [71] R. M. Haralick and J. Kart us. Arrangements, Homomorphisms, and Discrete Relaxation. IEEE Trans. On Systems, Man, and Cybernetics, SMC-8(8):600- 612, Aug. 1978. [72] R. M. Haralick and L. G. Shapiro. The Consistent Labeling Problem: Part 1. IEEE Trans. on Pattern Analysis and Machine Intelligence, PAMI-1(2):173- 184, Apr. 1979. [73] R. M. Haralick and L. G. Shapiro. The Consistent Labeling Problem: Part 2. IEEE Trans. on Pattern Analysis and Machine Intelligence, PAMI-2(3):193- 203, May 1980. [74] F. Harary. Graph Theory. Addison-Wesley, Reading, 1969. [75] W. S. Havens. A Theory of Schema Labelling. Computational Intelligence, 1(3 & 4):127-139, 1985. [76] T. C. Henderson. Discrete Relaxation Techniques. Oxford University Press, New York, 1989. [77) T. C. Henderson and L. S. Davis. Hierarchical Models and Analysis of Shape. Pattern Recognition, 14(1-6):197-204, 1981. [78] T. C. Henderson and A. Samal. Multiconstraint Shape Analysis. Image and Vision Computing, 4(2):84-96, May 1986. · [79] J. Hennessy. VLSI RISC Processors. VLSI Systems Design, 22- 32, Oct. 1985. [80) J. L. Hennessy. VLSI Processor Architecture. IEEE Trans. on Computers, C-33(12):1221-1246, Dec. 1984.
Reference URL	https://collections.lib.utah.edu/ark:/87278/s69s3s9x/99960