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Show CHAPTER 6 AN OPTIMAL LOOKAHEAD PROCESSOR TO PRUNE SEARCH SPACE In the previous chapters, the basic principles and procedures of solving a consistent labeling problem using the DRA heuristic were described. This chapter presents some recent work in developing parallel, tightly-mapped, special-purpose discrete relaxation VLSI computer architectures that dramatically decrease averagetime CLP search complexity. Except the effort to increase the strength of the constraints - the accuracy of the heuristic- this perhaps is the most important step to improve the DRA heuristic performance. Certainly, any parallel DRA algorithms can be easily mapped onto any generalpurpose multiprocessor computer system without much difficulty, as suggested by [120,162]. The major concern comes from the fact that there are serious problems with these machines, such as speedup saturation, very expensive overhead (incurred in process creation, synchronization and remote data communication), poor portability and movability (say, on a Robot) and high cost. Theoretically, there is a tremendous amount of data entropy between a problem structure and a generalpurpose computing structure (which may not be so serious for efficient problems). However, insofar as any general-purpose multiprocessor computers are able, none of the satisfactory speedups for AI search problems have been obtained. As was described in Section 1.3.2, we consider a special-purpose architecture (perhaps connected to a general-purpose host machine) a much more aggressive computing power |
