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Show 288 assumption is valid because a wire is characterized by a resistance and a capacitance which, in a given technology, both grow linearly with the length d; therefore, the time constant of the transistor load grows proportionally to tP. As noted by Chazelle and Monier in [21], the consequences of this effect are drastic. However, the asymptotics of VLSI have a much closer horizon than those of the Turing Machine. This horizon, in fact, is set by realistic bounds on the expectations -in the current technology- of minimum size and maximum chip size. Bilardi et al. investigated this interaction in which the wire parameters are weighted against the nonnegligible output impedance of the driving transistor and the input impedance of the driven transistor. They showed in [9] that a wire is modeled as a dispersive line of which the behavior of propagation, the electrical voltage, and current on the wire are described by a general wave equation. A solution of the wave equation is a function of both time and displacement. This model produces a solution that unifies mathematically all three above models. Bilardi et al. indicated that current MOS-FET VLSI technology falls in the domain of either the synchronous or the capactive model; in the latter, propagation delay is proportional to the length of the wires, provided that the minimum-sized driver transistors are employed. However, if the circuit ever becomes much faster or much larger than envisioned today, the logarithmic delay assumption should be modified. For example, consider the Josephson junction circuit assemblies built by IBM. They are lOcm on a side and run on a 1-3 ns clock. The wires in these circuits are superconductors [100]. In this case, Thompson [187] considers that the computational limitations of such enhanced technologies could be analyzed under Chazelle and Monier's linear delay assumption. This author implemented 1.0 J1. TriQuint GaAs technology for the PPL System in order to design GaAs circuits which could run as fast as several GHz [63]. It |