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Show 14 We see from Figure 6.3 (a) and Figure 6.3 (b) that the arc consistency checking between li ,k and those labels on object j is performed inside PE_A and PE..B, while the outer multiplication part of that equation is implemented in the horizontal arrays in Figure 6.4. It is also noted from Figures 6.3 and 6.4 that the DRA2 architecture can readily be extended to different numbers of objects and labels. For example, in Figure 6.4, an additional row array can be added in order to accommodate each additional label, and an additional column array can be added in order to accommodate each additional object. As the number of labels is increased, the number of input wires to each PE must be correspondingly increased because the input wires to each PE must equal m (the number of labels). Some simple design techniques can be used to vary the numbers of n and m by programming the DRA architecture. A critical analysis indicates that a monolithic DRA2 system for 8, 16, and 32 ·, objects is technically implementable in the 3.0 1-L NMOS, 2.0 1-L and 1.2 J.L CMOS, and 1.0 1-L GaAs processes [53]. 6.3.2 A Parallel SWD DRA2 Algorithm The parallel SIMD DRA2 algorithm run on the DRA2 architecture is shown in Figure 6.5. It works in the following sequence of six steps of operations: Operation 1: Initiation and Data Input. Before the DRA computation begins, a board of n x m labels and n2 sets of m x m constraint elements Ci,j must be input into the DRA2 architecture. All label elements, i.e., li,k, can be loaded in parallel if the number of pins permits; otherwise, it can be shifted in and out in a sequential manner. As explained before, since the DRA2 architecture aims at solving the regwn color identification problem, instead of inputting n2 label compatibility matrices, |
