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Show 134 transmission and propagation.2 This assumption is actually quite conservative and reliable. The second assumption concerns finding out and making use of practical, optimal "lower bounds." That is, in real engineering practice, the best technologies currently available are used to design and fabricate the architectures. For example, our PPL GaAs tool is capable of implementing a GaAs circuit whose clock speed could run around several hundred MHz to several GHz [63). Our wire interconnection technology,3 e.g., Mosaic's Series 2000 line of UNIPRO Silicon Circuit Boards, permits the system clock to run as high as 200 MHz [94) and Mosaic's Series 3000 line of UNIPRO Silicon Circuit Boards permits the maximum time delay across a 1" square UNIPRO segment (which is capable of interconnecting as many as 36 chips) in as low as 330 picoseconds [95). Depending on the technology (MOS or GaAs) applied, a clock speed exceeding 400 MHz or 600 MHz is achievable on the wafer scale [92]. Most previous work adopted n = m in their implementations. Assumption 6.3, therefore, provides a fair ground for comparing the performance of different algorithms and architectures. Assumption 6.4 requires the prototype implementations to be useful, at least, for some computer vision and image analysis applications. The last assumption stimulates a greater challenge for a very fast DRA computing architecture. 6.1.2 A Parallel Machine Model and Performance Measures In the case of uniprocessor machines, the computation model as defined by von Neumann is taken to be the standard. Several models have been proposed to study the computational properties of multiprocessors (see [155] for a survey). 2If a logarithmic time cost is assigned to the large fan-in and and or gates , for example, the clock period can be tuned to cover this delay. 3 Courtesy of Professor Bob Johnson, founder of MOSAIC, Inc. |
