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Show 251 patroller and Sibling {Label) Patroller. It takes both Patrollers 0(1) time to determine a traversal path in the depth-first order. 7 .3.4 The Search Space Pruning Engine This uses the DRA5 hardware heuristic architecture to prune search space. The worst case time complexity is O(nm). The detailed architecture designs for the DRAs were described in Chapter 6. In Figure 7.6, a DRA5 architecture can be identified as two blocks labeled L RAM Array and Search Space Pruning Engine. Note that the Search Space Pruning Engine is a Parallel C Memory Array superposed with an array of DRA processors. The C Memory Array can be shared among different search branches and this can be implemented in practice using MOSAIC technology. During the search processes, an intermediate labeling (or a solution labeling) first appears at the rightside of the Search Space Prune Engine and at the L RAM Array, the Solution Checker (in the Solution Memory) tests whether a solution has been found. If it is so, the solution is saved; otherwise, the intermediate labeling was fed into the DRA5 processor array for next iteration. 7 .3.5 The Parallel State Memory Often if massive parallelism does exist, memory management overheads constraint performance, i.e., massive parallelism implies massive data structures and massive data communication. The goal of the Parallel State Memory is for parallelizing sequential state saving and communication to provide fast searching and fast backtracking facilities. There are five control signals which are associated with a Parallel State Memory, i.e., R/W, transfer-down, back-transfer, transfer-to-dra and transfer-to- |
