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Show 115 of the gradient model versus a conceptual shared memory model. Another simulator, the Rediflow simulator, which simulates a proposed applicative system has been enhanced to incorporate the gradient model load balancing mechanism. Various architecture tradeoffs are studied using these two simulation tools. The results show that the gradient model performs satisfactorily. The reliability issue of applicative multiprocessor systems is another subject studied. We first propose the concept of functional checkpointing in contrast with conventional checkpointing schemes. Functional checkpointing is concise, asynchronous, fully distributed, and applicable over a wide range of static or dynamic load distribution techniques, including the gradient model. Two fault recovery techniques based on the notion of functional checkpointing are suggested. The thrust of these recovery models is to minimize the overhead while the system is in normal, error-free operation. The rollback recovery method attempts to reconstruct the faulty section of the program structure by redoing the functions from the most efficient parent task or tasks. In other words, the recovery starts from the closest capable functional checkpoints. The simple rollback method may be costly if a failure happens at the later stage of a program evaluation. The splice recovery scheme also utilizes the closest capable checkpoints for error recoveries as in the rollback method. In addition, the splice scheme tries to salvage as many intermediate partial results as possible. The salvage is made possible by a backward grandparent processor linkage and a program graph stamping method. This approach enables the parent tasks of a faulty processor to regenerate the corrupted portion of the program and splice the recovery results into the framework preceding the failure. A hierarchical task level stamping is introduced to improve the efficiency of practical implementation of the proposed schemes. The hierarchy is a topdown decomposition of the program graph. The decomposition uses the physical mapping of processors as the first layer. The second layer is the local stamping of a subtree tnside each processor. A subtree may be further split |
