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Show 65 Table 2: Breakdown of utilization by xputer processor ut switch ut Xptr max avg std max avg std 1 100.0 83.2 29.6 95.8 48.2 27.7 2 100.0 83.5 30.6 87.4 55.6 27.3 3 100.0 84.6 30., 87.8 55.7 26.3 4 100.0 82.7 28.2 88.2 50.9 27.8 5 100.0 81.4 28.3 87.4 51.2 26.0 6 100.0 83. 1 31.3 89.8 60.1 28.1 7 100.0 84.0 29.0 92.3 61.3 26.6 8 100.0 86.4 24.6 96.2 58.0 26.0 9 100.0 82.3 29. 1 94.6 49.6 25.9 10 100.0 82.9 30.3 95.7 59.5 28.3 11 100.0 82.5 30. 1 99.7 58.4 26.3 12 100.0 86.7 20.7 97.6 59.8 27.3 13 100.0 83.5 26.6 89.6 45.7 26. 1 14 99.8 82.8 31.1 86.8 53.7 25.4 15 100.0 83.6 28.8 78.9 51.8 23.6 16 100.0 81.6 28.4 91.9 52.0 27.3 2.6.3.7 _Communication speed. The results from the above simulations show that the switch utilization is well within our technology assumption, which assumes each communication channel has a 10 Megabits per second data transfer rate. Since communication overhead is a critical gauge in any mul- . tiprocessing system, this section examines the effect of communication bandwidth by changing the speed settings in the Rediflow simulator. The test program is still DC 1024 with wrapped 4 by 4 grid configuration. Figure 19 shows the impact of communication bandwidth on processor and switch utiliza-tions. The speedup of the system is depicted in Figure 20. Slow communication channels, e.g., 1 MHz, significantly impede the sys-tern throughput, since the processors are only utilized half of the time. The speedup increases as the communication bandwidth improves. However, when the channel races beyond the 10 MHz rate, the system starts to approach the throughput upper bound. This simulation shows that a communication channel speed of 10 MHz seems adequate for this combination of processors, switches, and task granularities. |
