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Show CHAPTER 7 CONCLUSIONS The sigma-delta modulator was successfully designed in ACME and simulated correctly. Two stages of decimation and a despreader were added to the sigma-delta modulator, and the complete chip simulated accurately using Hspice. Differential ECL/CML logic, which offers the highest speed performance, was used to implement the circuits, and the design was done in semicustom. This type of design gives the freedom to place the leaf cells (transistors, diodes, resistors and capacitors) anywhere in the chip, except for a restriction on the via ports which had to be within the metal 3 strips that ran across the chip. The chip was completed by connecting the metal 3 strips in the layout editor. Because of the decision to move to semicustom from gate-arrays, it was possible to add more functionality to the chip. This enabled that the final output rate could be brought down to 6.25 MHz, which can be directly fed into a 1.211 CMOS chip for further processing. A cell library was created using this design methodology, and the cells from this library can be used in fast and efficient implementation of similar circuits in the future. The Appendix shows some of the basic cells in the cell library that use three-level logic. They can be modified to be used for a four-level logic, which also use the same power levels(OV, -6.2V and -8.0V). 7.1 Future Research The present chip demonstrates the working of the sigma-delta modulator In HBTs along with the despreader. The chip needs to be sent out for fabrication and then tested to see the maximum speed that it can operate on. From Hspice si1nulations, the chip is estimated to run at 2 GHz oversampling rate. The present |
