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Show 7 To check the response of the sigma-d Ita rnodulator to an input signal of a certain bandwidth instead of a fixed frequency, an input which orr sponds to th Sine function was used. The data values for a Sine function were generat d using a program by using the appropriate frequency values in the formula Sin2?Tft/t. Thes data values were used to create a piece-wise linear voltage input to the sigma-delta modulator, and then the Spice simulation and the FFT were performed to obtain the spectrum of the output. The input spectrum of a Sine function is basically a pulse of bandwidth equal to the limiting or maximum frequency. The sigma-delta modulator was simulated for a pulse of bandwidth 10 MHz and the output spectrum of this simulation is shown in Figure 6.8. The 10 MHz pulse is converted without any distortion and all the quantization noise is at a higher frequency. This simulation is perfect for the chip, since the final output message is at a frequency of 6.25 MHz, which can completely be recovered, since it is less than the 10 MHz bandwidth. The simulation was also performed for a 100 MHz pulse, but the Sine function failed to give the right simulation, because as the pulse width increases to higher frequencies, the power of the function reduces drastically. 6.3 Stage I Simulation To simulate the Stage I decimator, the accumulator and the comparator had to be simulated first before connecting them together to form the accumulate and dump decimator. Figure 6.9 shows the Hspice simulation output for the counter. The accumulator has the same design as the counter, except for the additional circuitry which resets the counter when the count value reaches 20. Also the input data to the accumulator is now the data coming from the sigma- delta modulator. When this bit is a one, the accumulator acts like a counter and increments the value. When the bit is a zero, the accumulator basically stores the value like a register. When the clear signal goes high, it resets the accumulator just like the counter, thus enabling a new cycle of accumulate and dump. The counter simulation shows the clear pulse that it generates every 20 cycles and also shows the counter output increasing in value until it reaches 20, and then getting reset. |
