| OCR Text |
Show :32 4.4 ACME Design System ACME is a graphical design tool that imple1nents th hi rar hi al d ign trat gy known as "physical schematic capture." In this 1nethod th d sign r has dir t control on the actual physical placement of logic. In other words A ME provid san environment in which structural and physical design may take place sirnultan ously. Some of the useful features of ACME include facilities for design-time parasitic extraction, simulation models that include complex wiring models, and provisions for adding automatic design tools that use its hierarchical physical schematics. A very useful feature of ACME is the designer control over physical placement. As HBT technology advances and lithography shrinks devices, the device capacitance tends to decrease. Also, as the circuit gate delays are relatively small, the interconnect delays dominate overall circuit performance. Thus the direct control over all physical placement of both function and interconnect is of utmost irnportance to in1plement high performance circuits. All of the previous design in HBT at the University of Utah was done using ACME tools. A GaAs HBT gate-array cell library was already available in ACME, and this was a starting point for the design in this thesis. The initial plan was to design the sigma-delta modulator using the HBT gate-arrays using some of the cells that were already available in the cell library. These cells use three level ECL/CML current tree logic, and all signals (inputs and outputs) have differential logic. The initial design of the Opamp and Comparator in this thesis was done using these Gate Arrays, and hence it is worth looking into some of the concepts behind this design in the next section. 4.5 Gate Array Design HBT circuits can be categorized into two main logic families. They are the ernitter-coupled logic(ECL) and its variant, current mode logic(CML) and heterojunction integrated injection logic(HPL ). In circuit applications, the highest speed performance is achieved by using nonsaturating transistor operation as in ECL/CML. The gate array design here used the ECL/CML. In the ECL-type of |
