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Show v 0 L T D B L I N 1. BODE PLOT 151). 691) : : : : : : : : : : : : l :: COHP . AC 1 ::::.:~· T C T T L ·1 :L r·: T \!·~ -1 ~ 0. 0 ~-· ···+·····..f ·· .. · - . . ~.· ··· ·.f· · · ·~.· ·· ·+. · ··· i.· ·· · ·+. ·· ··.f · ·· .. +.· ······.f ···\\I. 1.·-~ -1 I) 0. 0 ~-····~· · ·· ·· .. ~·······~········~·······~········~·······~········:········~·······~········~····\t·~ -1 71) 0 i: i i i i i i i i i i i ~ i: - 1.0 100 . 0 lD.OK LOX lDD.OX 1D.OG 10.0H HERTZ CLOGJ 15.8~89G Figure 5.5. Bode Plot of Comparator The complete sigma-delta modulator design is shown in the Figure 5. 7. It contains two voltage level shifters which are used as references for the comparator and the latch, an RC integrator with two 20Kf! resistors connected to a 1.5pF capacitance, a comparator, a master-slave flip-flop used as the latch, and a single stage differential amplifier used for scaling. The inputs to the sigma-delta modulator are the analog signal, a reference voltage(-5.2V), and a level shifted clock that is running at the oversampling frequency. The output of the sigma-delta modulator is a differential pair of digital values varying between OV and -0.4V, which are the string of logic O's and 1 's that correlate to the analog input signal. |