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Show CHAPTER 5 DESIGN AND IMPLEMENTATION DETAILS In the previous chapter the semicustom design approach was discussed which was followed for the chip design, with some design details and comparison with the initial plan, the gate array design. This chapter will detail the complete design of the HBT chip starting from the design of an HBT opamp to building a sigma-delta modulator, to adding the digital circuitry to the back end of the sigma-delta modulator which includes the first stage decimator, the despreader and the second stage decimator. After individually discussions of the various components of the chip, the operation of the complete chip as a single unit will be discussed. The first phase of the design involved building an HBT Opamp with guaranteed stability, high gain, high bandwidth and a high slew rate, which are all very essential for operation of the sigma-delta modulator. Because of the high speed of operation of the sigma-delta modulator, high bandwidth was of extreme importance. Also due to the negative feedback in the integrator, the opamp had to be stable throughout the operating bandwidth. The integrator could be designed in two ways, either by using switched capacitors where sampling is done at discreet intervals of time, or as a continuous time integrator, using an RC combination. Due to the high speeds involved, a switched capacitor integrator would be too slow for its operation, and hence the continuous time integrator was chosen. The second task involved designing a high speed comparator which performs the two level quantization in the sigma-delta modulator. The opamp and the comparator were the main components of the sig1na-delta modulator, and significant care had to be taken in designing them. |
