| OCR Text |
Show 54 5.5 Despreader and Second Stage Decimator The output of the sigma-delta modulator after the first stage of decimation i a 5- bit number dumped out at Nyquist rate (20 times less than the sampling frequ ncy). These data contain the spread signal which has a much higher bandwidth than th actual message it contains. To obtain the signal, these data have to be despread using a PN code that is exactly the same as the one used to spread the original message before transmitting. The despreading is also exactly the same as spreading, and is nothing but a modulo-2 addition of the PN code to the data. This despreads the spread message and simultaneously spreads any interfering messages. The PN code generator is outside the chip and the 1 bit PN code is fed into the chip serially at the chip rate. Before despreading the 5-bit data, which range from 0-20, th.e number is scaled to a range of -10 to 10. Now, all that the despreader does is inverts the signal if the PN code is a 1, or keeps it the same when it is a 0. This also makes the design of the second stage accumulate and dump decimator easier. The despreader has a 6 bit adder, and multiplexers to do the scaling and the inversion in one step. The numbers are represented in two's complement form, and they can be simply added together for accumulation. The second stage decimator divides the frequency by a factor of 16. It contains a 9-bit register, a 4-bit counter and a 9-bit adder to accomplish the task of accumulate-and-dump for every cycle of 16. The counter gives out a clear signal every 16 cycles which loads in a new value into the register and dumps out the old value to the outside through the pads. This assumes that the PN code is at a frequency 16 times higher than the message signal, and hence the final 9-bit data coming out of the chip contains the actual message signal at 6.25MHz bandwidth. This is for a 2GHz sampling rate and a 100MHz spread spectrum signal. The 4-bit counter in this stage divides the clock further by a factor ~of 16 and sends out the new 6.25MHz clock to the outside. We also have the 100MHz clock connected to the pads tapped from the first stage decimator. Figure 5.10 contains the ACME design of the complete chip containing the de- |
