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Show 125 division step is to perform the evaluation of an entire level during one clock cycle. In this case, it takes d clock cycles to produce the result where d is the depth of the network. Evaluations of successive inputs can be pipelined. Although the result is delayed d clock cycles, the throughput of the pipelined network is the same as in the combinational evaluation. 5.2.3 Application in Arithmetic Logic Unit Using total differential to evaluate Boolean functions has other applications. One example can be found in the implementation of arithmetic logic units (ALU). A part of the ALU is the general logic function block [15, 56] which is essentially an implementation of a multiplexer with switches (see Figure 5.5). Four control signals, /o, / i , / 2, and f%, are needed to specify the operation performed by the total differential for the entire function intermediate total differentials Z l l l UBE UBE UBE UBE rr rr rr n input values Figure 5.4. A Network of UBEs |
