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Publication Type	technical report
School or College	College of Engineering
Department	Computing, School of
Creator	Chandramouli, V.
Title	Design of a Self-Timed, Pipelined, Floating Point Multiplier in Gallium Arsenide
Date	1994-06
Description	This thesis presents the design of a self-timed, floating point multiplier in Gallium Arsenide (GaAs) technology. It implements the Institute of Electrical and Electronic Engineers (IEEE) single precision standard. Self-timed design methodology offers some advantages over a synchronous approach, especially at higher clock frequencies, which are quite common in technologies like GaAs. This thesis looks at the various issues involved by undertaking the design of a system of reasonable complexity. It begins with a study of existing techniques for parallel binary multiplication. Based on this study, an architecture comparison is presented. Then a new architecture is obtained by modifying an existing architecture and compared against other competing approaches in terms of area and latency.; Also, as part of this thesis, a new family of precharged circuits has been developed that allows for a delay insensitive implementation in GaAs. Since delay insensitive systems tend to reflect the average case behavior rather than the worst case, this approach will improve performance in cases where applicable.; Finally, based on SPICE simulations, the proposed multiplier was sound to have a latency of 24ms and a peak throughput of 76 MFLOPS. It is also shown to have an area about one-third and consume about half the power of an existing GaAs floating point multiplier, described in the 1992 IEEE GaAs Symposium.
Type	Text
Subject	gallium arsenide; floating point multiplier; GaAs; GaAs technology
Language	eng
Bibliographic Citation	Chandramouli, V. (1994). Design of a self-timed, pipelined, floating point multiplier in gallium arsenide.
Series	University of Utah Computer Science Technical Report
Relation is Part of	ARPANET
Format Medium	application/pdf
Format Extent	74,241,242 bytes
File Name	Chandramouli-Design_Of.pdf
Conversion Specifications	Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display
ARK	ark:/87278/s60g5mcm
Setname	ir_computersa
ID	97163
Reference URL	https://collections.lib.utah.edu/ark:/87278/s60g5mcm

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Title	Page 133
Setname	ir_computersa
ID	97160
OCR Text	Show REFERENCES [1] AKELLA, V. An Integrated Framework for High-Level Synthesis of Self-Timed Circuits. PhD thesis, Dept. of Computer Science, Univ. of Utah, Dec. 1992. [2] BOOTH, A. D. A Signed Binary Multiplication Technique. Qt. J. Mech. Appl. Math. 4 (1951 ). [3] BROWN, R., ET AL. A 160,000 Transistor GaAs Microprocessor. IEEE International Solid State Circuits Conference. Session 5 - Microprocessors, Paper TA 5.5. [4] BRUNWAND, E. A Cell Set for Self-Timed Design using Actel FPGAs. Tech. Rep. UUCS-91-013, Dept. of Computer Science, University of Utah, Aug. 1991. [5] BURKS, A., GOLDSTINE, H., AND VON NEUMANN, J. Preliminary Discussion of the Logical Design of an Electronic Computing Instrument, 1946. [6] CHEN, M. C. The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI. IEEE Transactions on Computers 37, 3 (Mar. 1988). [7] DOBBERPUHL, D., ET AL. A 200 MHz 64 bit Dual-Issue CMOS Microprocessor. IEEE Journal of Solid-State Circuits 27, 11 (Nov. 1992). [8] EARLE, J. G. Latched Carry Save Adder, Mar. 1965. Published in IBM Technical Disclosures Bulletin. [9] EDWARDS, D. A Micropipelined Microprocessor, 1993. Private Communication. [10] FARIS, A., AND ROBERTSON, P. Source Follower Field-Effect Logic Gate (SFFL), Dec. 1989. U.S. Patent Number 4,885,480. [11] FLYNN, M. J ., AND WASER, S. Introduction to Arithmetic for Digital System Designers. CBS college publishing, 1982. [12] GoNCLAVES, N., AND H. DE MAN. NORA: A Race Free Dynamic CMOS Technique for Pipelined Logic Structures. IEEE Journal of Solid-State Circuits 18 (1990). [13] HAUCK, S. Asynchronous Design Methodologies: An Overview. Tech. Rep. 93-05-07, Dept. of Computer Science, Univ. of Washington, Seattle, 1993.
Reference URL	https://collections.lib.utah.edu/ark:/87278/s60g5mcm/97160