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Show 64 speed up could be obtained. A 12 bit adder was simulated in SPICE under similar conditions as the test chip. The one that came closest to the actual value was the version simulated under ss process corner and 25C and V bg=OV (in accordance with other test results). The simulated value was found to be 5.16ns. One must keep in mind that, owing to the poor testing environment, all signals were badly distorted and the edges were not clearly defined. Thus, the actually measured values from oscilloscope traces are not very accurate. The fact that the adder worked without buffers is an encouraging sign. This could offer considerable savings in power over DCFL. More analysis needs to be done to see how safe this design approach is. Finally, the working of the test circuits is a positive sign that this concept is indeed tenable. More research needs to be done to optimize and develop these circuits further. Since we can now build complex gates, one could build precharged versions of carry lookahead and Ling [25] adders and compare them with DCFL. 3.6 Summary In this chapter two logic families, both possible candidates for implementing the PAA scheme, were presented. The first one was DCFL, a well known, widely used logic family. The second one was a precharged logic family, similar to DCVSL in CMOS, developed as part of this thesis. A carry completion adder was simulated using this scheme and the speeds were comparable to DCFL but the power consumption was significantly lower. A time efficient way of generating the "done" signal that reduced the overhead in done detection was also presented. A test chip containing some precharged adder circuits was fabricated and all the precharged circuits were found to be functional. The precharged logic family offers some advantages over DCFL. It has better noise margins, gives a method for building complex gates which is not possible with DCFL and also gives us a way of building self-timed circuits in GaAs, consuming |
