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Show CHAPTER4 DESIGN OF THE MULTIPLIER ARRAY 4.1 Introduction In Chapter 3, an architecture was chosen for the multiplier after examining the various tradeoffs. In the last chapter, two logic families were presented: one was DCFL which is well known and the second one was a new one that could be used for implementing dual rail asynchronous systems. In this chapter, the implementation of the array part of the multiplier in ACME (A Cell Matrix Environment), a VLSI CAD tool under development in the dept, will be described. Before describing the implementation, however, a suitable logic family must be chosen. This is done in the next section. 4.2 Choosing a Logic Family As discussed in Chapter 1, the dual rail approach is expensive in terms of area because we now have to worry about routing two signal wires instead of one. However, it provides a clear performance advantage when the average case delay is significantly different than the worst case delay. The bundled data approach, on the other hand, always models the worst case delay. In an array multiplier, the critical path is the rippling of the sum signal along the diagonal. Since the sum signal depends on all three inputs to a CSA, schemes similar to carry look ahead or carry skip can not be used. Thus, it is not clear whether the average case delay of an array multiplier is significantly different from worst case delay of O(n). The architecture that we have chosen consists of subarray type multipliers |
