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Show 109 whereas the Vitesse process is a commercially available one. The architecture used in the existing multiplier is based on a full ( 4,2) tree based approach. It also uses Booth recoding. In Chapter 2, it was shown that the full tree based approach (with Booth recoding) achieves the minimum possible latency but at considerable investment in area. This is very clearly reflected in the table too. For n=24, the optimal approach would give the latency of the array to be 5 CSA delays whereas our approach has a latency of 10 CSA delays. In the table the latency for the new architecture is more than double possibly because of differences in the implementation of the Rounding/ CPA stage. The implementation details of this stage for the existing multiplier were not available. It is to be noted that under maximum utilization, the new approach fares much better with a throughput of 13ns. However, the area of the existing multiplier is more than three times the area of the new multiplier commensurate with the results of Chapter 2. This in spite of the fact that the new design has not used metal3 for routing outside of the cells because of an ACME constraint. The area estimate for the new multiplier was obtained as follows. From the ACME layout of the 8 x 24 multiplier an accurate estimation of the 24 x 24 array multiplier was obtained. Then the area of the Rounding/CPA stage was estimated by using the sizes of the precharged adder, other ACME cells, etc. The total area of the complete multiplier then came out to be about 18 sq.mm. However, to allow for a margin of error, this area was rounded up to 25 sq.mm. The logic family used in the existing multiplier was Source Follower FET Logic [1 0], a logic family that offers higher speed, better noise margins and consumes more power(about twice that of DCFL). Our approach uses DCFL whose merits are discussed in Chapter 3. The power estimation for our multiplier was obtained by counting the total number of gates and assuming 0.4m W /gate. Also, the various superbuffers used were taken into account and a margin for error was allowed. |
