Design of a Self-Timed, Pipelined, Floating Point Multiplier in Gallium Arsenide

This thesis presents the design of a self-timed, floating point multiplier in Gallium Arsenide (GaAs) technology. It implements the Institute of Electrical and Electronic Engineers (IEEE) single precision standard. Self-timed design methodology offers some advantages over a synchronous approach, especially at higher clock frequencies, which are quite common in technologies like GaAs. This thesis looks at the various issues involved by undertaking the design of a system of reasonable complexity. It begins with a study of existing techniques for parallel binary multiplication. Based on this study, an architecture comparison is presented. Then a new architecture is obtained by modifying an existing architecture and compared against other competing approaches in terms of area and latency.; Also, as part of this thesis, a new family of precharged circuits has been developed that allows for a delay insensitive implementation in GaAs. Since delay insensitive systems tend to reflect the average case behavior rather than the worst case, this approach will improve performance in cases where applicable.; Finally, based on SPICE simulations, the proposed multiplier was sound to have a latency of 24ms and a peak throughput of 76 MFLOPS. It is also shown to have an area about one-third and consume about half the power of an existing GaAs floating point multiplier, described in the 1992 IEEE GaAs Symposium.