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Show CHAPTER 5 DESIGN OF THE ROUNDING/CPA UNIT 5.1 Introduction So far in the previous chapters it has been shown how to reduce the 24 high partial product tree to two rows in the carry save form. However, this must be converted into a binary representation in order to be meaningful to the outside world. This is usually done using a carry propagate adder (CPA) at the final stage. In this chapter, the A in CPA stands for both addition and adder interchangeably. If this were unsigned integer multiplication, we would be done after this step. However, since we are doing floating point multiply, we are not done yet. In general a M X N multiplication would yield a product of M + N bits. In this case, it would be 48 bits. However, in the real world the number of bits of precision are usually fixed. Since the inputs were in the single precision format width of 24 bits, the result too must be rounded of to 24 bits. In this chapter some algorithms for rounding that can be carried out together with the final carry propagate addition are discussed. This discussion is based on Santoro's [34] work. However, the circuits discussed there are adapted here for GaAs and a self-timed implementation. 5.2 The Basic Rounding Algorithm The IEEE standard specifies four rounding modes :round to nearest, round towards +oo, round towards -oo and round towards zero. Of these the default rounding mode is round to nearest and in the case of a tie, round towards even. |
