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Show 115 used that detects it is done as soon as possible. Moreover, the regularity and power requirements of this adder are comparable to the ripple carry case. 6.4 Future Directions In this thesis, only a part of the multiplier was actually laid out and simulated. An immediate extension would be to build the entire circuit as outlined in this thesis and fabricate a test chip. That would give an asynchronous system of sufficient complexity to be actually built in GaAs. However, care must be taken to do a more exhaustive SPICE simulation of the circuits with better capacitance values and SPICE models. Most commercial high performance multipliers require an IEEE double precision implementation. An extension of this project might be to build a double precision multiplier using the PAA scheme in conjunction with Booth recoding as outlined in this thesis and compare the speed, area, power requirements of this multiplier with existing ones. This would also provide a testbed for the efficacy of the new PAA scheme. An interesting extension to this project is to build a synchronous version of this design and compare the issues in design. On a related note, one could also implement this in other technologies such as submicron CMOS and compare the speed differences. An important part of this thesis has been the development of a family of precharged circuits that could be used to implement dual rail systems in GaAs. However, more complex systems other than 8 bit ripple carry adders have to be built to evaluate this logic family's effectiveness. A 32 bit precharged carry skip CCS adder using the optimized version of the adder and the done detection circuit as described in this thesis could be built. Also, it would be interesting to see if a precharged Ling adder could be built. Based on a test chip, the advantages and disadvantages with respect to DCFL could be analyzed. If this approach seems cost effective, one could |
