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Show COLLEGE OF ENGINEERING Mac Wibbels Ken Stevens RELATIVE TIMING CONSTRAINT MAPPING FOR LOW POWER INTEGRATED CIRCUITS Mac Wibbels (Ken Stevens) Department of Electrical and Computer Engineering University of Utah The continued development of digital systems and improved methods of semiconductor fabrication have allowed computer systems to become integrated in society. Digital Systems and semiconductors are involved in a wide range of applications from business and education to recreation and entertainment. As the processing capabilities of digital systems have increased, the energy required to charge and discharge additional units of digital logic as well as the energy required to toggle the clock have led to significant challenges in power consumption. Low power asynchronous systems offer a promising alternative to current synchronous designs. Despite evidence that asynchronous circuits are capable of achieving higher performance in VLSI designs, asynchronous circuits have not gained much footing in the commercial semiconductor market. The reasons for the limited use of these systems are primarily the lack of design software for asynchronous circuits and the challenges involved in verifying the timing requirements of asynchronous units. Commercial EDA tools do not offer support for synthesis and optimization of asynchronous systems, which has stunted the development of asynchronous systems in commercial design. The goal of this research was to develop an application to automatically map constraints onto a design has not yet been developed. This project builds on Dr. Stevens'work in developing timing constraints for asynchronous systems. Utilizing his proposed method of relative timing constraints, Dr. Stevens is able to generate enhanced Synopsis Design Constraint (SDC) constraints for asynchronous circuits. The application uses enhanced SDC constraints and NET layouts in order to develop SDC constraints, which can be interpreted by synthesis software. With further development, the project will allow asynchronous designs, with an order of magnitude reduction in energy, to be designed with the same productivity as clocked designs. Asynchronous circuits have the potential to create substantial improvements in reducing the power consumption of digital systems. This project will assist in automating the synthesis of asynchronous systems, which have been demonstrated to achieve power reductions of 9 0 % or more. |
