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Show CHAPTER4 A DESIGN FOR OR-PARALLEL LOGIC PROGRAMMING ON THE BUTTERFLY This chapter describes the design of an OR-parallel logic programming implementation called Boplog (!!utterfly OR-:Earallel Logic). Many of the ideas were first presented in [48]. It begins with an overview in which the framework for the design is built, and then proceeds with a detailed discussion of the multiple-binding environment method and task migration strategy. It assumes a knowledge of the Warren Abstract Machine and the Butterfly consistent with their treatment in previous chapters. The last part of this chapter discusses some pragmatic issues which affect the success with which the design can be implemented. Of special importance for the Butterfly are memory management issues. The way memory is used is a central concem in the transformation of the design to a running system. 4.1 Overview The previous chapter noted the aspects of the Butterfly which distinguish it from other commercial shared-memory multiprocessors. Boplog is expressly designed to accommodate its drawbacks and capitalize on its strengths. Boplog is targeted for Butterfly systems with many processor nodes, and is designed to allow a correspondingly large physical memory to be accessed. The design tends to stress speed over space. Within reason, where a choice between faster execution and better memory usage needs to be made, speed is favored. However, the ability to use the potentially huge physical memory of the Butterfly is important for investigating the performance of the implementation on large problems on large machines. |
