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Show 48 object's memoxy. The user can specify explicitly which SARto use by passing its SAR number to the function, or can instruct the system to use any free SAR from those allocated to the user's process. The virtual address of any byte in the object can be computed by additions to the base address returned by Map_Obj. Any reference to such a virtual address is passed to the PNC by the 68020, where it is converted to its corresponding physical address and the memory access is performed. There are 512 SARs in each PNC, of which up to 256 (in powers of two) may be used by a process using a buddy-system allocation scheme. The total addressing capacity of a process is determined by the 256 SARs, each of which may indicate the start of a 64 kilobyte object. Thus, at any time a process may only address 16 megabytes of memory (256 SARs x 64 kilobytes/SAR); on a fully-configured Butterfly with 4 megabytes on each of 256 nodes, this accounts for only 1/64 of the available memory. Furthermore, the l1m1t of 512 SARs per node makes it impossible to have several processes with large address spaces on each node. If more than these 16 megabytes are to be addressed, the values stored in the SARs must be changed to re-map the memory system. This can be accomplished using the operating system functions Map_Obj and Unmap_Obj. Unmap_Obj decrements the OAB reference count of the object and frees the SAR associated with the object by its Map_Obj call. As shown in Table 1•. these functions are rather slow. Using them to re-map memory dynamically is clearly impractical. 3.3 Using the Butterfly for Logic Programming The architecture of the Butterfly clearly should be considered when designing applications to use it. The architecture profoundly influences the design of the ORparallel system described here. Most important to the design is the shared memory aspect of the Butterfly. Potentially, all of the physical memory can be shared by all processes, using dynamic ·Results in Table 1 are for 500 consecutive in-line Map_Obj and Unmap_Obj in alternation, using an explicit SAR number, with the OlD and virtual address in machine registers, and with interrupts inhibited. The time for instruction fetches from local memory is included. |
