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Show 17 Accurately modeling a processor with a cache or pipeline would require more than simply incrementing the clock by the nominal execution time for each instruction. Subroutine calls could be inserted to model dynamic behavior that significantly affects performance. By performing timing analysis at the machine level, strategy B is amenable to timing models of arbitrary ac cura cy and complexity. The main disadvantage of strategy B is the inherent nonportability of assembly language programming. Different processors (and different compilers) may have incompatible parameter passing mechanisms. Translating m target assembly languages to n host assembly languages would require m times n translators .'· In addition, care must be taken that the insertion of timing instructions does not change the control flow of the program. Since the timing probes affect the condition code settings, indiscriminate placement of probes is fatal to the correct behavior of the program. One possible solution is to insert additional instructions that first save the condition codes immediately prior to the execution each timing probe and subsequently restore the condition codes following the execution of the timing probe. The practicality of this solution will vary from processor to processor and other solutions may be needed. In general, the difficulties of implementing strategy B make it less desirable as a processor model for Simon. However, this strategy is simple to implement for one special case: when the host and target processor are the same. This special case requires no translation, but simply the insertion of timing probes. Moreover, if the timing probes are limited to simple clock increments, then only the undesirable side effects of condition code setting *Of -course, the number of translators could be reduced by trans lat ing f irst to an intermediate language and then translating to the host assembler [17], but th is st i ll requ ires cons iderable effort in the support of portability. ** In this case one could use the realt ime clock of the processor to est imate the execut ion timings. However, if the instruction t1mmgs are small compared to the c lock units (e.g., microseconds vs. milliseconds), then strategy B may be much more accurate than the rea ltime clock timings. |
