An A-FPGA architecture for relative timing based asynchronous designs

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Publication Type pre-print
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Manoranjan, Jotham Vaddaboina
Title An A-FPGA architecture for relative timing based asynchronous designs
Date 2014-01-01
Description This paper presents an asynchronous FPGA architecture that is capable of implementing relative timing based asynchronous designs. The architecture uses the Xilinx 7-Series architecture as a starting point and proposes modifications that would make it asynchronous design capable while keeping it fully functional for synchronous designs. Even though the architecture requires additional components, it is observed when implemented on the 64-nm node, the area of the slice was increases marginally by 7%. The architecture leaves configurable routing structures untouched and does not compromise on performance of the synchronous architecture.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Volume 7032497
First Page 1
Last Page 6
Language eng
Bibliographic Citation Manoranjan, J. V., & Stevens, K. S. (2014). An A-FPGA architecture for relative timing based asynchronous designs. 2014 International Conference on Reconfigurable Computing and FPGAs, 7032497, 1-6.
Rights Management (c) 2014 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 377,429 bytes
Identifier uspace,19391
ARK ark:/87278/s6p30787
Setname ir_uspace
Date Created 2015-04-13
Date Modified 2021-05-06
ID 712915
Reference URL https://collections.lib.utah.edu/ark:/87278/s6p30787
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