Rethinking DRAM design and organization for energy-constrained multicores

DRAM vendors have traditionally optimized for low cost and high performance, often making design decisions that incur energy penalties. For example, a single conventional DRAM access activates thousands of bitlines in many chips, to return a single cache line to the CPU. The other bits may be accessed if there is high locality in the access stream. Otherwise significant energy is wasted, especially when memory access locality is reduced as core, thread, and socket counts increase. Instead we propose and analyze two optimizations which activate as little of the DRAM circuitry as possible, while incurring only modest performance penalties. The first approach, Selective Bitline Activation (SBA), is compatible with existing DRAM standards. SBA waits for both RAS and CAS signals to arrive before activating exactly those bitlines that provide the requested cache line. Our second proposal, Single Subarray Access (SSA), re-organizes the layout of DRAM subarrays and the mapping of data to subarrays so that the entire cache line is fetched from a single subarray. Since SSA reads an entire cache line from a single DRAM, we also examine the addition of DRAM checksums, to increase error detection and correction capabilities. The approach is similar to existing methods used on disk drives. We then provide chipkill-level reliability through RAID techniques. The SSA design yields memory energy savings of 6X, while incurring an area cost of 4.5%, and even improving performance by up to 15%. Our chipkill solution has significantly lower capacity and energy overheads than other known chipkill solutions, while incurring only an 11% performance penalty compared to an SSA memory system without chipkill.