Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Kitai, Tomoya; Oguro, Yusuke; Yoneda, Tomohiro; Mercer, Eric |
Title |
Level oriented formal model for asynchronous circuit verification and its efficient analysis method |
Date |
2002 |
Description |
Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits. On the other hand, in order to use such a model on large circuits, techniques to avoid the state explosion problem must be developed. This paper first introduces a level-oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
1 |
Last Page |
9 |
Language |
eng |
Bibliographic Citation |
Kitai, T., Oguro, Y., Yoneda, T., Mercer, E., & Myers, C. J. (2002). Level oriented formal model for asynchronous circuit verification and its efficient analysis method. Pacific Rim International Symposium on Dependable Computing, 1-9. November. |
Rights Management |
(c) 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
460,733 bytes |
Identifier |
ir-main,15020 |
ARK |
ark:/87278/s6cj8z3d |
Setname |
ir_uspace |
ID |
706983 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6cj8z3d |