Realizing burstmode circuits via STG speed independent synthesis

This report discusses the similarities and differences of STG and Burstmode specifications and synthesis methods. The first part of the report examines the applicability and efficiency of STG's single controller fork-join concurrency ability versus Burstmode's partitioned fork-join concurrency approach. Results comparing the synthesis results for designs using the same level of concurrency in the controllers (STG and Burstmode), as well as the different methods of realizing fork-join concurrency, are presented. The second part compares the timing assumptions being made by the SI synthesis algorithms and if they can generate a hazard-free solution under Burstmode burst property and fundamental mode assumptions. This comparison shows that speed independent generalized C-element implementations exhibit hazards under the burst property assumption model and can thus not be used to implement Burstmode controllers. It also shows that the SI standard C-element approach, while complying with the burst property of a legal Burstmode specification, may not generate - from a Burstmode point of view - minimum covers. In addition, timed circuits are analyzed for the same hazard considerations. Timed circuits have the same problems as SI when it comes to Burstmode hazard considerations. An extension to timed circuit synthesis that potentially can reduce the number of entrance violations in a standard C-element implementation significantly is also presented.