Filters: Department: "Computing, School of" Collection: "ir_uspace" Type: "Text" Format: "application/pdf"
| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 226 |
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Grodstein, Joel | User's manual for the sisyphus simulation environment | This report describes how to create and simulate a design with Sisyphus. Inasmuch as Sisyphus is written in Symbolics-Lisp, some familiarity with both Lisp and with Symbolics computers is presumed. In addition, the concepts presented here presume an acquaintance with [3]. First, a disclaimer ? this... | Sisyphus; Simulation environment; Symbolics-Lisp; Symbolics computers | 1986 |
| 227 |
 |
Gopalakrishnan, Ganesh | Peephole optimization of asynchronous networks through process composition and burst-mode machine generation | In this paper we discuss the problem of improving the e ciency of macromodule networks generated through asynchronous high level synthesis We compose the behaviors of the modules in the sub network being optimized using Dill s trace theoretic operators to get a single behavioral description for ... | Macromodule networks; Peephole; Asynchronous networks | 1993 |
| 228 |
 |
Gopalakrishnan, Ganesh | Verifying a virtual component interface-based PCI bus wrapper using an LSC-based specification | Because of the high stakes involved in integrating externally developed intellectual property (IP) cores used in System on Chip (SOC) designs, methods and tool support for quick, easy, decisive standard compliance verification must be developed. Such methods and tools include formal standard spec... | System on Chip; SOC; Verification; PCI bus wrapper; LSC | 2002-01-22 |
| 229 |
 |
Balasubramonian, Rajeev | Microarchitectural techniques to reduce interconnect power in clustered processors | The paper presents a preliminary evaluation of novel techniques that address a growing problem - power dissipation in on-chip interconnects. Recent studies have shown that around 50% of the dynamic power consumption in modern processors is within on-chip interconnects. The contribution of interc... | Microarchitectural techniques; Interconnect power; Clustered processors; On-chip | 2004 |
| 230 |
 |
Riloff, Ellen M. | Exploiting strong syntactic heuristics and co-training to learn semantic lexicons | We present a bootstrapping method that uses strong syntactic heuristics to learn semantic lexicons. The three sources of information are appositives, compound nouns, and ISA clauses. We apply heuristics to these syntactic structures, embed them in a bootstrapping architecture, and combine them with... | Syntactic heuristics; Semantic lexicons; Bootstrapping method; Appositives; Compound nouns; ISA clauses; Co-training | 2002 |
| 231 |
 |
Henderson, Thomas C. | Knowledge-based 2-D vision system synthesis | A knowledge-based approach to computer vision provides the needed flexibility for performing recognition and inspection of objects in a complex environment. A system is described which uses knowledge about the environment, sensors, and performance requirements to construct a functional configuratio... | 2-D vision system | 1987 |
| 232 |
 |
Weinstein, David | Cache-rings for memory efficient isosurface construction | Processor speeds continue to increase at faster rates than memory speeds. As this performance gap widens, it becomes increasingly important to develop "memory-conscious" algorithms - programs that still optimize instruction count and algorithmic complexity, but that also integrate optimizations for ... | Processor speeds; Memory speeds; Computer memory; Cache-rings | 1997 |
| 233 |
 |
Lindstrom, Gary E. | Using a functional language and graph reduction to program multiprocessor machines or functional control of imperative programs | This paper describes an effective means for programming shared memory multiprocessors whereby a set of sequential activities are linked together for execution in parallel. The glue for this linkage is provided by a functional language implemented via graph reduction and demand evaluation. The full ... | shared memory multiprocessors; Programming; functional language; graph reduction; Demand evaluation | 1991 |
| 234 |
 |
Balasubramonian, Rajeev | CHOP: adaptive filter-based DRAM caching for CMP server platforms | As manycore architectures enable a large number of cores on the die, a key challenge that emerges is the availability of memory bandwidth with conventional DRAM solutions. To address this challenge, integration of large DRAM caches that provide as much as 5× higher bandwidth and as low as 1/3rd of... | CHOP; DRAM caching; CMP server platforms; Manycore architectures; Hot page; Filter cache; Multi-core processors | 2010 |
| 235 |
 |
Sobh, Tarek M.; Henderson, Thomas C. | A dynamic recursive structure for intelligent exploration | We suggest a new approach for inspection and reverse engineering applications. In particular, we investigate the use of discrete event dynamic systems (DEDS) to guide and control the active exploration and sensing of mechanical parts for industrial inspection and reverse engineering. We introduce dy... | Intelligent exploration; Discrete event dynamic systems; DEDS; Dynamic recursive finite state machines; DRFSM | 1992 |
| 236 |
 |
Jacobson, Hans | Realizing burstmode circuits via STG speed independent synthesis | This report discusses the similarities and differences of STG and Burstmode specifications and synthesis methods. The first part of the report examines the applicability and efficiency of STG's single controller fork-join concurrency ability versus Burstmode's partitioned fork-join concurrency appr... | Burstmode circuits; STG | 1997 |
| 237 |
 |
Bruderlin, Beat | Constraint objects ? integrating constraint definition and graphical interaction | This paper describes the implementation of a new constraint??based tech?? nique for direct manipulation in interactive CAD which will simplify the design process especially in the early stages We introduce so called Constraint Objects and Parameter Objects which constitute an object??oriented ... | Constraint objects | 1992 |
| 238 |
 |
Balasubramonian, Rajeev | Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches | In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uniform cache architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this ... | Page coloring; Shadow-memory addresses; Cache capacity allocation; Data/page migration; Last level caches; Non-uniform cache architectures (NUCA) | 2009-02 |
| 239 |
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Sobh, Tarek M.; Henderson, Thomas C. | Robotic prototyping environment (Progress report) | Prototyping is an important activity in engineering. Prototype development is a good test for checking the viability of a proposed system. Prototypes can also help in determining system parameters, ranges, or in designing better systems. The interaction between several modules (e.g., S/W, VLSI, CAD,... | Prototyping; Prototyping environment; Robotic prototyping | 1994 |
| 240 |
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Gopalakrishnan, Ganesh | Towards a verification technique for large synchronous circuits | We present a symbolic simulation based veri cation approach which can be applied to large synchronous circuits A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based veri cation... | symbolic simulation; verification | 1992 |
| 241 |
 |
Freire, Juliana; Silva, Claudio T. | Querying and creating visualizations by analogy | While there have been advances in visualization systems, particularly in multi-view visualizations and visual exploration, the process of building visualizations remains a major bottleneck in data exploration. We show that provenance metadata collected during the creation of pipelines can be reused ... | Provenance; VisTrails; Pipelines; Query-by-example | 2007-11 |
| 242 |
 |
Lindstrom, Gary E. | Combinator evaluation of functional programs with logical variables | A technique is presented that brings logical variables into the scope of the well known Turner method for evaluating normal order functioned programs by S, K, I combinator graph reduction. This extension is illustrated by SASL+LV, an extension of Turner's language SASL in which general expressions s... | Functional programs; Logical variables; SASL+LV; Turner's language | 1987 |
| 243 |
 |
Riloff, Ellen M. | Recognizing and organizing opinions expressed in the world press | Tomorrow's question answering systems will need to have the ability to process information about beliefs, opinions, and evaluations-the perspective of an agent. Answers to many simple factual questions-even yes/no questions-are affected by the perspective of the information source. For example... | Opinions; Opinion recognition; World press; MPQA project; Multiple perspectives | 2003 |
| 244 |
 |
Greer, William Harvey | Monaural sensitivity to dispersion in impulses and speech | Monaural sensitivity; Dispersion; Impulses; Speech | 1975 | |
| 245 |
 |
Smith, Kent F. | PPL design examples (NMOS30 Version) | This work was supported in part by Defense Advanced Research Projects Agency under Contract number DAAK1184K0017. All opinions, findings, conclusions or recommendations expressed in this document are those of the author(s) and do not necessarily reflect the views of DARPA. | Circuits; Design | 1986 |
| 246 |
 |
Gopalakrishnan, Ganesh | hopCP: A concurrent hardware description language | hopCP is a language for the specification, simulation, and synthesis of hardware systems. hopCP captures the behavior of a hardware system by specifying the causal relationships between actions that the system can perform. No specific timing discipline is implied by a hopCP specification. Hence, hop... | hopCP; Hardware systems | 1991 |
| 247 |
 |
Evans, David | Graphical man/machine communications: December 1971 | Semi-Annual Technical Report for period 1 June 1971 to 31 December 1971. This document includes a summary of research activities and facilities at the University of Utah under Contract F30602-70-C-0300. Information conveys important research milestones attained during this period by each of the f... | Man/machine communications; Computing systems; Digital waveform processing | 1971-12 |
| 248 |
 |
Henderson, Thomas C.; Cohen, Elaine | Innate theories as a basis for autonomous mental development | Sloman (in robotics), Chomsky and Pinker (in natural language), and others, e.g., Rosenberg (in human cooperative behavior) have proposed that some abstract theories relevant to cognitive activity are encoded genetically in humans. The biological advantages of this are (1) to reduce the learning ... | Autonomous mental development | 2009 |
| 249 |
 |
Archuleta, Michael | Hidden surface line drawing algorithm | This paper describes a fast procedure in processing hidden surface pictures with the output in vector form. The program has been written expressly for a Decsystem 10 and has performed successfully on three different installations. The algorithm which is being used is a modification to the Watkins' A... | Watkins algorithm; Hidden surface | 1972 |
| 250 |
 |
Richardson, William F.; Brunvand, Erik L. | The NSR processor prototype | The NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr... | Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor | 1992 |