Cache-rings for memory efficient isosurface construction

Update Item Information
Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Weinstein, David
Title Cache-rings for memory efficient isosurface construction
Date 1997
Description Processor speeds continue to increase at faster rates than memory speeds. As this performance gap widens, it becomes increasingly important to develop "memory-conscious" algorithms - programs that still optimize instruction count and algorithmic complexity, but that also integrate optimizations for data locality and cache performance. In this paper we present a topological isosurface extraction algorithm which utilizes a "cache-ring" data structure to optimize memory performance. We compare our algorithm to an analogous edge-hashing algorithm which, though functionally equivalent, gives less priority to memory performance. While our algorithm actually executes more instructions during execution, we nonetheless see a speed-up over the traditional method, as we more-than-compensate for the extra instructions with superior memory performance.
Type Text
Publisher University of Utah
First Page 1
Last Page 18
Subject Processor speeds; Memory speeds; Computer memory; Cache-rings
Subject LCSH Computer storage devices; Cache memory
Language eng
Bibliographic Citation Weinstein, D. (1997). Cache-rings for memory efficient isosurface construction. 1-18. UUCS-97-016.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 3,798,477 bytes
Identifier ir-main,16247
ARK ark:/87278/s65t441z
Setname ir_uspace
ID 706442
Reference URL https://collections.lib.utah.edu/ark:/87278/s65t441z
Back to Search Results