| Description |
Tiler is a special interactive editor used for designing VLSI circuits using the Path Programmable Logic (PPL) methodology. PPL cells are inserted into a rectangular grid by typing characters that represent the cells. Each available cell will have a character that represents it, but some characters might not have a cell "defined". When a character is typed that has no PPL cell defined for it, an appropriate error message will be displayed. All ordinary printable characters are assumed to be associated with PPL cells. The exact cell that is associated with each character will depend on which TECHNOLOGY has been specified. When tiler is first started, the user is prompted for the technology to be used for designing a PPL circuit. When a technology name is given by the user, a technology file is loaded into tiler. This file contains information about the process used to define the PPL cells (NMOS, CMOS, GaAs, etc.), the number of row and column wires in each PPL cell, the spacing of cells on the PPL grid, and information about each of the cells that are defined for the given technology. |
