Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Madan, Niti |
Title |
Exploiting eager register release in a redundantly multi-threaded processor |
Date |
2006 |
Description |
Due to shrinking transistor sizes and lower supply voltages, transient faults (soft errors) in computer systems are projected to increase by orders of magnitude. Fault detection and recovery can be achieved through redundancy. Redundant multithreading (RMT) is one attractive approach to detect and recover from these errors. However, redundant threads can impose significant performance overheads by competing with the main program for resources such as the register file. In this paper, we propose using eager register release in the main program thread by exploiting the availability of register values in the trailing thread's register space. This performance optimization can help support a smaller register file and potentially reduce register file access time, power consumption, and increase its immunity towards soft errors. |
Type |
Text |
Publisher |
Workshop on Architectural Reliability |
Volume |
39 |
First Page |
1 |
Last Page |
9 |
Subject |
Transient faults; Soft errors; Redundant multithreading; Eager register release; Register file design |
Subject LCSH |
Redundancy (Engineering) |
Language |
eng |
Bibliographic Citation |
Madan, N., & Balasubramonian, R. (2006). Exploiting eager register release in a redundantly multi-threaded processor. 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO- 39, 1-9. Orlando, December. |
Rights Management |
(c) Madan, N., & Balasubramonian, R. |
Format Medium |
application/pdf |
Format Extent |
106,817 bytes |
Identifier |
ir-main,12006 |
ARK |
ark:/87278/s6417fkr |
Setname |
ir_uspace |
ID |
705836 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6417fkr |